S9S08SG16E1MTL NXPの
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S9S08SG16E1MTL NXPの This addendum identifies changes to Rev. 8.1 of the MC9S08SG32 data sheet (covering MC9S08SG32 and MC9S08SG16). The changes described in this addendum have not been implemented in the specified pages. 1 Update to the “Nonvolatile Register Summary” table for NVFTRIM and NVOPT For the NVFTRIM and NVOPT registers in Table 4-4, “Nonvolatile Register Summary,” all reserved bits should be marked as “—” (not “0”). 2 Update to the “Instruction Set Summary” table for BRA and BRN In Table 7-2, “Instruction Set Summary,” remove “(if I = 1)” from the BRA instruction and remove “(if I = 0)” from the BRN instruction. The BRA and BRN instructions do not depend on the I bit.
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